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HM628127HB series 1 m high speed sram (128-kword 8-bit) ade-203-350d (z) rev. 4.0 nov. 1997 description the HM628127HB is an asyncronous high speed static ram organized as 128-k word 8-bit. it realize high speed access time (15/20 ns) with employing 0.8 m m shrink cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. the HM628127HB is packaged in 400-mil 32-pin soj for high density surface mounting. features single 5 v supply access time 15/20 ns (max) completely static memory ? no clock or timing strobe required equal access and cycle times directly ttl compatible ? all inputs and outputs 400-mil 32-pin soj package center v cc and v ss type pinout ordering information type no. access time package HM628127HBjp-15 HM628127HBjp-20 15 ns 20 ns 400-mil 32-pin plastic soj (cp-32db) HM628127HBljp-15 HM628127HBljp-20 15 ns 20 ns
HM628127HB series 2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a3 a2 a1 a0 cs i/o1 i/o2 v v i/o3 i/o4 we a16 a15 a14 a13 ss a4 a5 a6 a7 oe i/o8 i/o7 v v i/o6 i/o5 a8 a9 a10 a11 a12 cc (top view) HM628127HBjp/hbljp series cc ss pin description pin name function a0 to a16 address input i/o1 to i/o8 data input/output cs chip select oe output enable we write enable v cc power supply v ss ground
HM628127HB series 3 block diagram i/o1 . . . i/o8 we input data control column i/o column decoder memory matrix 256 rows 512 columns 8 bit (1,048,576 bits) row decoder oe cs cs cs v cc v ss cs a3 a2 a1 a0 a7 a6 a5 a4 a13 a12 a11 a14 a15 a16 a10 a9 a8 (lsb) (msb) (lsb) (msb) function table cs oe we mode v cc current i/o ref. cycle h standby i sb , i sb1 high-z l h h output disable i cc high-z l l h read i cc dout read cycle (1) to (3) l h l write i cc din write cycle (1) l l l write i cc din write cycle (2) note: : h or l
HM628127HB series 4 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc C0.5 to +7.0 v voltage on any pin relative to v ss v t C0.5* 1 to v cc +0.5 v power dissipation p t 1.0* 2 /1.5* 3 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c storage temperature under bias tbias C10 to +85 c notes: 1. v t min = C2.5 v for pulse width (under shoot) 10 ns 2. at still air condition 3. at air flow 3 1.0 m/s recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc * 2 4.5 5.0 5.5 v v ss * 3 000v input voltage v ih 2.2 v cc + 0.5 v v il C0.5* 1 0.8 v notes: 1. v il min = C2.0 v for pulse width (under shoot) 10 ns 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level.
HM628127HB series 5 dc characteristics (ta = 0 to +70 c, v cc = 5v 10%, v ss = 0v) parameter symbol min typ* 1 max unit test conditions input leakage current ii li i2 m a vin = v ss to v cc output leakage current ii lo i2 m a vin = v ss to v cc operation power supply current 15 ns cycle i cc 120 180 ma cs = v il , lout = 0 ma other inputs = v ih /v il 20 ns cycle i cc 100 150 standby power supply current 15 ns cycle i sb 55 100 ma cs = v ih , other inputs = v ih /v il 20 ns cycle i sb 4580 i sb1 2 mav cc 3 cs 3 v cc - 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc - 0.2 v * 2 * 2 0.2* 2 output voltage v ol 0.4 v i ol = 8 ma v oh 2.4 v i oh = C4 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and not guaranteed. 2. this characteristics is guaranteed only for l-version. capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 6 pf vin = 0 v input/output capacitance* 1 c i/o 8 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
HM628127HB series 6 ac characteristics (ta = 0 to +70 c, v cc = 5v 10%, unless otherwise noted.) test conditions input pulse levels: 0 v to 3.0 v input rise and fall time: 3 ns input and output timing reference levels: 1.5v output load: see figures (including scope and jig) dout 255 w 480 w 5 v 30 pf dout 255 w 480 w 5 v 5 pf output load (b) (for t clz , t olz , t chz , t ohz , t whz , and t ow ) output load (a) read cycle HM628127HB-15 HM628127HB-20 parameter symbol min max min max unit notes read cycle time t rc 15 20 ns address access time t aa 15 20 ns chip select access time t acs 15 20 ns output enable to outpput valid t oe 8 10ns output hold from address change t oh 55ns chip select to output in low-z t clz 33ns1 output enable to output in low-z t olz 11ns1 chip deselect to output in high-z t chz 7 7 ns1 output disable to output in high-z t ohz 7 7 ns1 chip selection to power up time t pu 00ns chip selection to power down time t pd 15 20 ns
HM628127HB series 7 write cycle HM628127HB-15 HM628127HB-20 parameter symbol min max min max unit notes write cycle time t wc 15 20 ns address valid to end of write t aw 12 15 ns chip select to end of write t cw 10 12 ns 9 write pulse width t wp 10 12 ns 8 address setup time t as 00ns6 write recovery time t wr 00ns7 data to write time overlap t dw 8 10 ns data hold from write time t dh 00ns write disable to output in low-z t ow 33ns1 output disable to output in high-z t ohz 7 7 ns1 write enable to output in high-z t whz 7 7 ns1 note: 1. transition is measured 200 mv from steady voltage with load (b). this parameter is sampled and not 100% tested. 2. address should be valid prior to or coincident with cs transition low. 3. we and/or cs must be high during address transition time. 4. if cs and oe are low during this period, i/o pins are in the output state. then, the data input signals of opposite phase to the outputs must not be applied to them. 5. if the cs low transition occurs simultaneously with the we low transition or after the we transition, output remains a high impedance state. 6. t as is measured from the latest address transition to the later of cs or we going low. 7. t wr is measured from the earlier of cs or we going high to the first address transition. 8. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low. a write ends at the earliest transition among cs going high and we going high. t wp is measured from the beginning of write to the end of write. 9. t cw is measured from the later of cs going low to the end of write.
HM628127HB series 8 timing waveforms read timing waveform (1) ( we = v ih ) t t t t t rc aa acs oe clz valid data address cs dout valid address high impedance t ohz oe t oh t chz t olz read timing waveform (2) ( we = v ih , cs = v il , oe = v il ) t t rc aa valid data address dout valid address t oh t oh
HM628127HB series 9 read timing waveform (3) ( we = v ih , cs = v il , oe = v il )* 2 valid data cs dout high impedance high impedance v cc supply current i cc i sb 50% 50% t pu t clz t acs t rc t chz t pd write timing waveform (1) ( we controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs * 3 t ohz * 4 * 4 oe high impedance* 5
HM628127HB series 10 write timing waveform (2) ( cs controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs * 3 t whz t ow * 4 * 4 high impedance* 5
HM628127HB series 11 low v cc data retention characteristics (ta = 0 to 70 c) this characteristics is guaranteed only for l-version. parameter symbol min typ* 1 max unit test conditions v cc for data retention v dr 2.0 v v cc 3 cs 3 v cc C 0.2 v (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v data retention current i ccdr 2 80 m av cc = 3 v, v cc 3 cs 3 v cc C 0.2 v (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 5 ms note: 1. typical values are at v cc = 3.0 v, ta = 25 c, and not guaranteed. low v cc data retention timing waveform cc v 4.5 v 2.2 v 0 v cs t cdr t r v 3 cs 3 v ?0.2 v cc cc dr v data retention mode
HM628127HB series 12 package dimensions HM628127HBjp/hbljp series (cp-32db) 20.71 21.08 max 32 17 116 0.74 10.16 0.13 11.18 0.13 3.50 0.26 0.43 0.10 9.40 0.25 2.85 0.12 1.30 max 0.10 1.27 0.80 +0.25 ?.17 hitachi code jedec eiaj weight (reference value) cp-32db conforms conforms 1.2 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
HM628127HB series 13 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
HM628127HB series 14 revision record rev. date contents of modification drawn by approved by 0.0 sep. 9, 1995 initial issue y. saitou k. yoshizaki 1.0 nov. 15, 1995 deletion of HM628127HB-25 series y. saitou k. yoshizaki 2.0 jun. 27 1996 change of format change of block diagram function table addition of mode parameter recommended dc operating conditions change of note 2. addition of note 3. ac characteristics change order of notes change of timing waveform addition of read timing waveform(2), (3) low v cc data retention characteristics change of test conditions for i ccdr y. saitou a. ide 3.0 nov. 19, 1996 change of package dimensions y. saitou a. ide 4.0 nov. 1997 change of subtitle

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